Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processing system that executes programs, such as, communication and multimedia programs. A processing system for such products may include multiple processors, memory for storing instructions and data, controllers, peripheral devices, such as communication interfaces, and fixed function logic blocks configured, for example, on a single chip. At the same time, portable products have a limited energy source in the form of batteries that are often required to support high performance operations from the processing system. To increase battery life, when possible, it is desired to perform these operations at reduced power levels. Many personal computers are also being developed to support high performance operations at low power drain to reduce overall energy consumption.
Internal to the processing system, the multiple processors may be configured in a number of different organizations, such as, an asymmetric multiprocessing organization that allows selective load balancing between the multiple processors which may be different and optimized to a particular system function or process, such as video, graphics, or communication processing. The processing functions may be portioned into a number of threads or tasks that are scheduled for execution on selected processors. A thread is considered the smallest individually schedulable process or sequence of instructions which may run in parallel with another thread. In the context of the present invention, a thread and a task may be used interchangeably. Tasks or threads may be sub-functions that are generally assigned to a processor by an operating system (OS) scheduler, for example, to meet performance requirements associated with system functions. Since the power associated with executing a task is a function of frequency, switching capacitance, and the square of the supply voltage, reducing power use generally requires a reduction in at least one of these variables. To more fully optimize power use, many processing systems have control over frequency and operating voltage in one or more circuit domains of power use. Due to the demanding nature of various functions, such as video, graphics, and communication, operating on portable devices, the multiple processors may be required to operate at gigahertz frequencies in order to meet a product's requirements. Since the functional demands on the processing system vary, the operating frequency is generally adapted to the existing system requirements. In a similar manner, reducing voltage, affects not only the power but also the operating frequency of the affected logic and memory devices, which in turn then affects how the frequency is controlled.
As circuit densities increase with each new technology generation, power loss during idle or standby conditions has also increased. Circuit leakage current tends to also increase with increasing circuit densities becoming more and more a source of significant power loss. To achieve increased densities and shorter circuit device delays that allow higher clock frequencies, internal circuit devices' threshold voltage is typically reduced. Reducing the threshold voltage generally increases the leakage current, which also is affected by process variations and temperature. A significant portion of a high density chip's energy use may be attributable to leakage current.
At an operating system scheduler level, task assignment in a multiprocessing system is a difficult problem even within a nominal operating environment having chips manufactured with consistent process characteristics (P) and operating within a constant and nominal operating voltage (V) and a nominal temperature (T), usually referred to as a nominal PVT environment. The problem of assigning tasks becomes even more difficult due to the nature of portable devices since they may use multiple chips manufactured with different processes and may also experience wide variations in the process characteristics within chips and between chips, use of different operating voltages which may be controllable, and be subjected to wide variations in ambient temperature. The variations in PVT generally have a dramatic affect on a chip's power utilization, including dynamic and static leakage power.